1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and a method for driving the same for performing a precharge operation.
2. Description of the Related Art
In general, a semiconductor device such a dynamic random access memory (DRAM) enters an active mode or a standby mode in response to a command inputted from an external device.
For example, a read operation or a write operation is performed during the active mode. When the read operation is performed, data is read from a memory cell, and when the write operation is performed, data inputted from the external device is written on the memory cell. If the active mode is terminated, the standby mode may be performed. During the standby mode, a data input/output path is precharged with a given voltage level such that data loaded on the input/output path in the active mode is prevented from being maintained. Thus, during a subsequent active mode, a read operation or a write operation will be performed sufficiently.
FIG. 1 is a circuit diagram illustrating a read path of a conventional semiconductor device.
Referring to FIG. 1, a semiconductor 100 includes a voltage supply unit 110, a bit line sense amplifying unit 120, a coupling unit 130, a first precharge unit 140, a second precharge unit 150, a local line driving unit 160 and a local line sense amplifying unit 170.
The voltage supply unit 110 drives a high voltage supply terminal PS and a low voltage supply terminal NS with a bit line precharge voltage VBLP during the standby mode, and drives the high voltage supply terminal PS with a core voltage VCORE and the low voltage supply terminal NS with a ground voltage VSS during the active mode, in response to a first enable signal SAP, a second enable signal SAN and a first precharge signal SADRVPCG.
The voltage supply unit 110 supplies the bit line precharge voltage VBLP as a source voltage and a sink voltage of the bit line sense amplifying unit 120 during the standby mode. The supply voltage unit 110 supplies the core voltage VCORE as the source voltage of the bit line sense amplifying unit 120 and the ground voltage VSS as the sink voltage thereof during the active mode. The bit line precharge voltage VBLP has a voltage level corresponding to a half of the core voltage VCORE.
The bit line sense amplifying unit 120 is coupled between the high voltage supply terminal PS and the low voltage supply terminal NS, and senses and amplifies data loaded on a pair of bit lines BL and BLB during the active mode. More specifically, the bit line sense amplifying unit 120 senses data of a memory cell MC on the pair of bit lines BL and BLB during the active mode, and amplifies the sensed data to a voltage level of the core voltage VCORE and the ground voltage VSS. The bit line sense amplifying unit 120 is disabled by the bit line precharge voltage VBLP provided through the high voltage supply terminal PS and the ground voltage supply terminal NS during the standby mode.
The coupling unit 130 selectively couples the pair of bit lines BL and BLB to a pair of segment lines SIO and SIOB in response to a column selection signal YI. More specifically, the coupling unit 130 transmits the data on the pair of bit lines BL and BLB, which are sensed and amplified by the bit line sense amplifying unit 120 to the pair of segment lines SIO and SIOB in response to the column selection signal VI.
The first precharge unit 140 precharges the pair of segment lines SIO and SIOB with the bit line precharge voltage VBLP in response to a second precharge signal BLEQ during the standby mode. More specifically, the first precharge unit 140 is coupled between the pair of segment lines SIO and SIOB, and precharges the pair of segment lines SIO and SIOB with the bit fine precharge voltage VBLP in response to the second precharge signal BLEQ, which is activated during the standby mode. Meanwhile, since the pair of bit lines BL and BLB are precharged with the bit line precharge voltage VBLP during the standby mode, the pair of segment lines SIO and SIOB are precharged with the bit line precharge voltage VBLP to minimize a leakage current caused by a transistor included in the coupling unit 130.
The second precharge unit 150 precharges the pair of segment lines SIO and SIOB with the core voltage VCORE in response to a third precharge signal SIOPCG during an initial period of the active mode. More specifically, the second precharge unit 150 is coupled between the pair of segment lines SIO and SIOB, and precharges the pair of segment lines SIO and SIOB with the core voltage VCORE in response to the third precharge signal SIOPCG, which is activated during the initial period of the active mode. A voltage level of the pair of segment lines SIO and SIOB is increased from the bit line precharge voltage VBLP to the core voltage VCORE for a sufficient operation of the local line driving unit 160 during the active mode.
The local line driving unit 160 transmits the data on the pair of segment lines SIO and SIOB to a pair of local lines LIO and LIOB in response to a third enable signal LSAEN. The local line driving unit 160 may be provided to overcome a loading concern since pairs of segment lines (not shown) are coupled to the pair of local lines LIO and LIOB.
The local line sense amplifying unit 170 senses and amplifies the data on the pair of local lines LIO and LIOB, and transmits the amplified data to a global line GIO. That is, the local line sense amplifying unit 170 amplifies the data on the pair of local lines LIO and LIOB with a given voltage, and transmits the amplified data to the global line GIO.
Hereinafter, an operation of the conventional semiconductor device shown in FIG. 1 will be described as below.
Firstly, the operation of the standby mode of the convention semiconductor will be described as below.
If the standby mode is performed, the voltage supply unit 110 drives the high voltage supply terminal PS and the low supply terminal NS with the bit line precharge voltage VBLP in response to the first precharge signal SADRVPCG. Thus, the bit line sense amplifying unit 120 is disabled since the high voltage supply terminal, e.g., a source voltage terminal, of the bit line sense amplifying unit 120 has a same voltage level as the low voltage supply terminal, e.g., a sink voltage terminal, of the bit line sense amplifying unit 120. The first precharge unit 140 precharges the pair of segment lines SIO and SIOB with the bit line precharge voltage VBLP in response to the second precharge signal BLEQ. Since the pair of bit lines BL and BLB are precharged with the bit line precharge voltage, the leakage current of the transistor included in the coupling unit 130 may be minimized by precharging the pair of segment lines SIO and SIOB with the bit line precharge voltage VBLP. The second precharge unit 150 is disabled in response to the third precharge signal SIOPCG.
Next, the operation of the active mode of the convention semiconductor device will be described.
If the active mode is performed, the voltage supply unit 110 drives the high voltage supply terminal PS with the core voltage VCORE in response to the first enable signal SAP, and drives the low voltage supply terminal NS with the ground voltage VSS in response to the second enable signal SAN. Thus, the bit line sense amplifying unit 120 senses and amplifies the data on the pair of bit lines BL and BLB. The second precharge unit 150 precharges the pair of segment lines SIO and SIOB with the core voltage VCORE in response to the third precharge signal SIOPCG during the initial period of the active mode. That is, the pair of segment lines SIO and SIOB are precharged with the core voltage VCORE instead of the bit line precharge voltage VBLP for a sufficient operation of the local line driving unit 160 during the active mode. Herein, the first precharge unit 140 is disabled. The coupling unit 130 transmits the data on the pair of bit lines BL and BLB in response to the column selection signal YI. The local line driving unit 160 transmits the data on the pair of segment lines SIO and SIOB to the pair of local lines LIO and LIOB. The local line sense amplifying unit 170 amplifies the data on the pair of local lines LIO and LIOB with a given voltage and transmits the amplified data to the global line GIO.
However, in the aforementioned conventional semiconductor device 100, an off-current may occur in the transistor included in the second precharge unit 150 during the standby mode. The core voltage VCORE is provided to a source of the transistor of the second precharge unit 150, and the bit line precharge voltage VBLP is provided to a drain of the transistor of the second precharge unit 150. Thus, since a current path is formed between a core voltage VCORE terminal and a bit line precharge voltage VBLP terminal of the conventional semiconductor device 100 during the standby mode, a leakage current may occur.
FIG. 2 is a block diagram illustrating an expanded read path of the conventional semiconductor device shown in FIG. 1.
As shown in FIG. 2, the pairs of segment lines SIO<1:M> and SIOB<1:M> are arranged in a plurality of memory cells MAT<1:N> A large amount of leakage current may occur in the conventional semiconductor device 100 by second precharge units coupled to the pairs of segment lines SIO<1:M> and SIOB<1:N> during the standby mode.